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Asynchronous Mips Processors: Educational Simulations, Robert L. Webb 2010 California Polytechnic State University - San Luis Obispo

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses and Project Reports

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous ...


Polyenvi, Stephen Beard, Josh Engel, Paul Fake, Diego Flores, Alvaro Nunez, Miguel Wong 2010 California Polytechnic State University - San Luis Obispo

Polyenvi, Stephen Beard, Josh Engel, Paul Fake, Diego Flores, Alvaro Nunez, Miguel Wong

Electrical Engineering

Poor indoor air quality is a problem that is recognized by the Environmental Protection Agency (EPA) to cause health issues. In order to raise awareness of this problem, this document outlines the construction of a device that economically measures air quality through five metrics: dust, smoke, ozone, humidity, and temperature. The device integrates with a router to provide users access to information about their indoor air quality anywhere over the internet as well as local access to the data via an LCD mounted on the router. By increasing indoor air quality awareness, this device will aid users in making adjustments ...


K-Delta-1-Sigma Modulators For Wideband Analog-To-Digital Conversion, Vishal Saxena 2010 Boise State University

K-Delta-1-Sigma Modulators For Wideband Analog-To-Digital Conversion, Vishal Saxena

Boise State University Theses and Dissertations

As CMOS technology scales, the transistor speed increases enabling higher speed communications and more complex systems. These benefits come at the cost of decreasing inherent device gain, increased transistor leakage currents, and additional mismatches due to process variations. All of these drawbacks affect the design of high-resolution analog-to-digital converters (ADCs) in nano-CMOS processes. To move towards an ADC topology useful in these small processes a first-order K-Delta-1-Sigma (KD1S) modulator-based ADC was proposed. The KD1S topology employs inherent time-interleaving with a shared integrator and K-quantizing feedback paths and can potentially achieve significantly higher conversion bandwidths when compared to the traditional ...


A Fully Integrated High-Temperature, High-Voltage, Bcd-On-Soi Voltage Regulator, Benjamin Matthew McCue 2010 University of Tennessee, Knoxville

A Fully Integrated High-Temperature, High-Voltage, Bcd-On-Soi Voltage Regulator, Benjamin Matthew Mccue

Masters Theses

Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a ...


Determination Of Material Emission Signatures By Ptr-Ms And Their Correlations With Odor Assessments By Human Subjects, Kwanghoon Han 2010 BEESL Lab., Syracuse University

Determination Of Material Emission Signatures By Ptr-Ms And Their Correlations With Odor Assessments By Human Subjects, Kwanghoon Han

Kwanghoon Han

The objectives of this study were to determine volatile organic compound (VOC) emission signatures of nine typical building materials by using proton transfer reaction-mass spectrometry (PTR-MS) and to explore the correlation between the PTR-MS measurements and the measurements of acceptability by human subjects. VOC emissions from each material were measured in a 50-l small-scale chamber. Chamber air was sampled by PTR-MS to determine emission signatures. Sorbent tube sampling and TD-GC/MS analysis were also performed to identify the major VOCs emitted and to compare the resulting data with the PTR-MS emission signatures. The data on the acceptability of air quality ...


Global Positioning Logger, Matthew Hall 2010 California Polytechnic State University - San Luis Obispo

Global Positioning Logger, Matthew Hall

Computer Engineering

The Global Positioning Logger (GPL) is a mobile embedded device that utilizes GPS technology. The GPS data is used to display current speed and past global locations.


A Graduate Education In Software Management And The Software Business For Mid-Career Professionals, Ray Bareiss, Gladys Mercier 2010 Carnegie Mellon University

A Graduate Education In Software Management And The Software Business For Mid-Career Professionals, Ray Bareiss, Gladys Mercier

Ray Bareiss

Given the unique nature of the software business, the faculty of Carnegie Mellon University’s Silicon Valley campus concluded that mid-career software professionals would be better served by a tailored master’s degree focusing on software management and more broadly on the business of software than by a typical MBA. Our software management master’s program integrates business, technical, and soft skills to prepare our students for technical leadership in their current companies or in entrepreneurial ventures. Our initial program built on the strengths of Carnegie Mellon’s world-class software engineering education. We targeted students working in large companies, engaged ...


Coaching Via Cognitive Apprenticeship, Ray Bareiss, Martin Radley 2010 Carnegie Mellon University

Coaching Via Cognitive Apprenticeship, Ray Bareiss, Martin Radley

Ray Bareiss

At Carnegie Mellon’s Silicon Valley campus we employ a learn by- doing educational approach in which nearly all student learning, and thus instruction, is in the context of realistic, team based projects. Consequently, we have adopted coaching as our predominant teaching model. In this paper we reflect on our experience with the nature of teaching by coaching using a framework derived from Cognitive Apprenticeship, and explain how we employ the techniques it suggests in our teaching. We also discuss a range of instructional tensions that arise in teaching by coaching and present a survey of student attitudes regarding the ...


On The Radiation-Induced Soft Error Performance Of Hardened Sequential Elements In Advanced Bulk Cmos Technologies, Norbert Seifert, Vinod Ambrose, B Gill, Q Shi, R Allmon, Charles H. Recchia, S Mukherjee, N Nassif, J Krause, J Pickholtz, A Balasubramanian 2010 SelectedWorks

On The Radiation-Induced Soft Error Performance Of Hardened Sequential Elements In Advanced Bulk Cmos Technologies, Norbert Seifert, Vinod Ambrose, B Gill, Q Shi, R Allmon, Charles H. Recchia, S Mukherjee, N Nassif, J Krause, J Pickholtz, A Balasubramanian

Charles H Recchia

No abstract provided.


On The Radiation-Induced Soft Error Performance Of Hardened Sequential Elements In Advanced Bulk Cmos Technologies, Norbert Seifert, Vinod Ambrose, B Gill, Q Shi, R Allmon, Charles H. Recchia, S Mukherjee, N Nassif, J Krause, J Pickholtz, A Balasubramanian 2010 Worcester Polytechnic Institute

On The Radiation-Induced Soft Error Performance Of Hardened Sequential Elements In Advanced Bulk Cmos Technologies, Norbert Seifert, Vinod Ambrose, B Gill, Q Shi, R Allmon, Charles H. Recchia, S Mukherjee, N Nassif, J Krause, J Pickholtz, A Balasubramanian

Physics Faculty Publications

No abstract provided.


Scalable, Memory-Intensive Scientific Computing On Field Programmable Gate Arrays, Salma Mirza 2010 University of Massachusetts Amherst

Scalable, Memory-Intensive Scientific Computing On Field Programmable Gate Arrays, Salma Mirza

Masters Theses 1911 - February 2014

Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for many scientific computing problems. This is due to the memory bottleneck that is encountered with large arrays that must be stored in dynamic RAM. A system of FPGAs, with a large enough memory bandwidth, and clocked at only hundreds of MHz can outperform a CPU clocked at GHz in terms of floating point performance. An FPGA core designed for a target performance that does not unnecessarily exceed the memory imposed bottleneck can then be distributed, along ...


Approaches To Multiprocessor Error Recovery Using An On-Chip Interconnect Subsystem, Ramakrishna P. Vadlamani 2010 University of Massachusetts Amherst

Approaches To Multiprocessor Error Recovery Using An On-Chip Interconnect Subsystem, Ramakrishna P. Vadlamani

Masters Theses 1911 - February 2014

For future multicores, a dedicated interconnect subsystem for on-chip monitors was found to be highly beneficial in terms of scalability, performance and area. In this thesis, such a monitor network (MNoC) is used for multicores to support selective error identification and recovery and maintain target chip reliability in the context of dynamic voltage and frequency scaling (DVFS). A selective shared memory multiprocessor recovery is performed using MNoC in which, when an error is detected, only the group of processors sharing an application with the affected processors are recovered. Although the use of DVFS in contemporary multicores provides significant protection from ...


Design Techniques To Improve Time Dependent Dielectric Breakdown Based Failure For Cmos Circuits, Emanuel S. Tarog 2010 California Polytechnic State University – San Luis Obispo

Design Techniques To Improve Time Dependent Dielectric Breakdown Based Failure For Cmos Circuits, Emanuel S. Tarog

Master's Theses and Project Reports

This project investigates the failure of various CMOS circuits as a result of Time Dependent Dielectric Breakdown (TDDB) and explores design techniques to increase the mean time to failure (MTTF) of large-scale circuits. Time Dependent Dielectric Breakdown is a phenomenon where the oxide underneath the gate degrades as a result of the electric field in the material. Currently, there are few well documented design techniques that can increase lifetime, but with a tool chain I created called the MTTF Analyzing Program, or MAP, I was able to test circuits under various conditions in order to identify weak links, discover relationships ...


Embedded Systems As Datacenters, Robert Iannucci 2009 RAI Laboratory LLC

Embedded Systems As Datacenters, Robert Iannucci

Robert A Iannucci

No abstract provided.


The Effect Of The Digit Slicing Architecture On The Fft Butterfly, Yazan Samir, Rozita Teymourzadeh 2009 Faculty of Engineering, Technology and Built Environment UCSI University

The Effect Of The Digit Slicing Architecture On The Fft Butterfly, Yazan Samir, Rozita Teymourzadeh

Dr. Rozita Teymourzadeh, CEng.

Most communications systems tend to achieve bandwidth, power and cost efficiencies to capable to describe modulation scheme. Hence for signal modulation orthogonal frequency division multiplexing (OFDM) transceiver is introduced to cover communications demand in four generation. However high performance Fast Fourier Transforms (FFT) as a main heart of OFDM acts beyond the view. In order to achieve capable FFT, design and realization of its efficient internal structure is key issues of this research work. In this paper implementation of high performance butterfly for FFT by applying digit slicing technique is presented. The proposed design focused on the trade-off between the ...


Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok VH 2009 Faculty of Engineering, Technology and Built Environment UCSI University

Vlsi Implementation Of Novel Class Of High Speed Pipelined Digital Signal Processing Filter For Wireless Receivers, Rozita Teymourzadeh, Yazan Samir, Shabuil Islam, Masuri Othman, Mok Vh

Dr. Rozita Teymourzadeh, CEng.

The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation ...


Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller, Hoe CK, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R 2009 Faculty of Engineering, Technology and Built Environment UCSI University

Design Of Automatic Soil Humidity Control Using Maximum Power Point Tracking Controller, Hoe Ck, Vaithlingam A.C., Rozita Teymourzadeh, Rajkumar R

Dr. Rozita Teymourzadeh, CEng.

The photovoltaic system uses the photovoltaic array as a source of electrical power for the direct conversion of the sun’s radiation to direct current without any environmental hazards. The main purpose of this research is to design of a converter with Maximum Power Point Tracker (MPPT) algorithm for any typical application of soil humidity control. Using this setup the major energy from the solar panel is used for the control of soil humidity. The design of the converter with MPPT together with the soil humidity control logic is presented in this paper. Experimental testing of the design controller is ...


On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok VH 2009 Faculty of Engineering, Technology and Built Environment UCSI University

On-Chip Implementation Of Pipeline Digit-Slicing Multiplier-Less Butterfly For Fast Fourier Transform Architecture, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam, Mok Vh

Dr. Rozita Teymourzadeh, CEng.

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This study presents on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly, digit-slicing multiplier-less single constant technique was utilized in the critical path of Radix-2 Decimation In Time (DIT) FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was ...


On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman 2009 Faculty of Engineering, Technology and Built Environment UCSI University

On-Chip Implementation Of High Resolution High Speed Floating Point Adder/Subtractor With Reducing Mean Latency For Ofdm, Rozita Teymourzadeh, Yazan Samir, Nooshin Mahdavi, Masuri Othman

Dr. Rozita Teymourzadeh, CEng.

Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high resolution high speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critical path and decrease the latency, the novel structure was designed and investigated. Consequently ...


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