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Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories, Shruti S. Vyas 2011 University of Massachusetts Amherst

Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories, Shruti S. Vyas

Masters Theses 1911 - February 2014

NAND flash memories are popular due to their density and lower cost. However, due to serial access, NAND flash memories have low read and write speeds. As the flash sizes increase to 64GB and beyond, searches through flash memories become painfully slow. In this work we present a hardware design enhancement technique to speed-up search through flash memories. The basic idea is to generate a small signature for every memory block and store them in a signature block(s). When a search is initiated, signature block is searched which produces reference of possible blocks where data might be contained, reducing ...


Robust Signaling Techniques For Through Silicon Via Bundles, Krishna Chaitanya Chillara 2011 University of Massachusetts Amherst

Robust Signaling Techniques For Through Silicon Via Bundles, Krishna Chaitanya Chillara

Masters Theses 1911 - February 2014

3D circuit integration is becoming increasingly important as one of the remaining techniques for staying on Moore’s law trajectory. 3D Integrated Circuits (ICs) can be realized using the Through Silicon Via (TSV) approach. In order to extract the full benefits of 3D and for better yield, it has been suggested that the TSVs should be arranged as bundles rather than parallel TSVs. TSVs are required to route the signals through different dies in a multi-tier 3D IC. TSVs are excellent but scarce electrical conductors. Hence, it is important to utilize these resources very efficiently.

In high performance 3D ICs ...


Testable Clock Distributions For 3d Integrated Circuits, Michael T. Buttrick 2011 University of Massachusetts Amherst

Testable Clock Distributions For 3d Integrated Circuits, Michael T. Buttrick

Masters Theses 1911 - February 2014

The 3D integration of dies promises to address the problem of increased die size caused by the slowing of scaling. By partitioning a design among two or more dies and stacking them vertically, the average interconnect length is greatly decreased and thus power is reduced. Also, since smaller dies will have a higher yield, 3D integration will reduce manufacturing costs. However, this increase in yield can only be seen if manufactured dies can be tested before they are stacked. If not, the overall yield for the die stack will be worse than that of the single, larger die.

One of ...


On Process Variation Tolerant Low Cost Thermal Sensor Design, Spandana Remarsu 2011 University of Massachusetts Amherst

On Process Variation Tolerant Low Cost Thermal Sensor Design, Spandana Remarsu

Masters Theses 1911 - February 2014

Thermal management has emerged as an important design issue in a range of designs from portable devices to server systems. Internal thermal sensors are an integral part of such a management system. Process variations in CMOS circuits cause accuracy problems for thermal sensors which can be fixed by calibration tables. Stand-alone thermal sensors are calibrated to fix such problems. However, calibration requires going through temperature steps in a tester, increasing test application time and cost. Consequently, calibrating thermal sensors in typical digital designs including mainstream desktop and notebook processors increases the cost of the processor. This creates a need for ...


Multicore, Multithreaded, Phase-Synchronous Fm Sound Synthesizer, Justin Tomlin 2011 California Polytechnic State University - San Luis Obispo

Multicore, Multithreaded, Phase-Synchronous Fm Sound Synthesizer, Justin Tomlin

Electrical Engineering

This project implements a phase-synchronous FM synthesis algorithm in hardware. Envelope and low frequency oscillator modulation of oscillator parameters is implemented. The microcontroller the system is based on, the XMOS XS1-G4, allows for physical parallelism including features such as multiple cores, multiple hardware threads on each core, a hardware event-driven thread scheduler, and channel, channel ends, and link switches for thread and core communication. The event-driven architecture of this device was ideal for implementing this synthesis algorithm. The final product is portable, durable, has a simple, intuitive user interface, and allows for extensive spectral shaping capabilities. The basic functional requirements ...


Switching Energy-Delay Of All Spin Logic Devices, Srikant Srinivasan 2010 Purdue University

Switching Energy-Delay Of All Spin Logic Devices, Srikant Srinivasan

Srikant Srinivasan

A recent proposal called all spin logic (ASL) proposes to store information in nanomagnets that communicate with spin currents in order to construct spin based digital circuits. We present a coupled magnetodynamics/spin-transport model for ASL devices that is based on established physics and is benchmarked against available experimental data. This model is used to show the linear dependence of switching energy and quadratic dependence of energy-delay of ASL devices on the number of Bohr magnetons comprising a nanomagnet. A scaling scheme that could lower the energy-delay of spin-torque switching while maintaining thermal stability is discussed.


Contextualized Mobile Support For Learning By Doing In The Real World, Ray Bareiss, Natalie Linnell, Martin Griss 2010 Carnegie Mellon University

Contextualized Mobile Support For Learning By Doing In The Real World, Ray Bareiss, Natalie Linnell, Martin Griss

Ray Bareiss

This research addresses the use of mobile devices with both embedded and external sensors to provide contextualized help, advice, and remediation to learners engaged in real-world learn-by-doing tasks. This work is situated within the context of learning a complex procedure, in particular emergency responders learning to conduct urban search and rescue operations. Research issues include the design and delivery of contextualized performance support and the inferring of learner actions and intentions from sensor data to ensure that the right support is delivered just in time, as it is relevant to what the learner is doing.


Fpga Implementation Of Pipeline Digit-Slicing Multiplier-Less Radix 2 2 Dif Sdf Butterfly For Fast Fourier Transform Structure, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam 2010 Faculty of Engineering, Technology and Built Environment UCSI University

Fpga Implementation Of Pipeline Digit-Slicing Multiplier-Less Radix 2 2 Dif Sdf Butterfly For Fast Fourier Transform Structure, Yazan Samir, Rozita Teymourzadeh, Masuri Othman, Shabiul Islam

Dr. Rozita Teymourzadeh, CEng.

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 22 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly multiplier, digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-22 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon ...


Optimised Toolbox For The Design Of Rotary Reluctance Motors, Grace I, Rozita Teymourzadeh, Bright S, Aravind CV 2010 Faculty of Engineering, Technology and Built Environment UCSI University

Optimised Toolbox For The Design Of Rotary Reluctance Motors, Grace I, Rozita Teymourzadeh, Bright S, Aravind Cv

Dr. Rozita Teymourzadeh, CEng.

Operation of the rotary reluctance machine is highly affected due to the sequential attraction-repulsion principle of the adjacent phase excitation. The problem has been identified and addressed by various researchers in the past decades. Effective magnetic design is one way of minimizing the effect. However it is tedious and time consuming as the design procedure involve higher analytical derivation and calculations. This paper presents a simpler graphical user interface toolbox to use for the design of reluctance motors. The developed interface calculates the analytical values of the aligned, unaligned and intermediate inductance values so that the user can interpret the ...


Arithmetic Units For The Elliptic Curve Cryptography With Concurrent Error Detection Capability, Arash Hariri 2010 The University of Western Ontario

Arithmetic Units For The Elliptic Curve Cryptography With Concurrent Error Detection Capability, Arash Hariri

Electronic Thesis and Dissertation Repository

The elliptic curve cryptography is an important branch in public-key cryptography. In this thesis, we consider the elliptic curve cryptography over binary extension fields from two different points of view. First, we investigate the underlying arithmetic operations in the elliptic curve cryptography. The main arithmetic operation is the scalar multiplication. This operation is based on two elliptic curve operations, known as the point addition and point doubling. Implementing these two elliptic curve operations requires finite field arithmetic, specifically, finite field addition, multiplication, squaring, and inversion. We focus on two finite field operations, namely finite field multiplication and squaring. For the ...


Design And Implementation Of A Signal Conditioning Operational Amplifier For A Reflective Object Sensor, Ankit Master 2010 University of Tennessee - Knoxville

Design And Implementation Of A Signal Conditioning Operational Amplifier For A Reflective Object Sensor, Ankit Master

Masters Theses

Industrial systems often require the acquisition of real-world analog signals for several applications. Various physical phenomena such as displacement, pressure, temperature, light intensity, etc. are measured by sensors, which is a type of transducer, and then converted into a corresponding electrical signal. The electrical signal obtained from the sensor, usually a few tens mV in magnitude, is subsequently conditioned by means of amplification, filtering, range matching, isolation etc., so that the signal can be rendered for further processing and data extraction.

This thesis presents the design and implementation of a general purpose op amp used to condition a reflective object ...


An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri 2010 University of Tennessee, Knoxville

An Fpga Based Implementation Of The Exact Stochastic Simulation Algorithm, Phani Bharadwaj Vanguri

Masters Theses

Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which uses differential equations to describe the chemical interactions. However, such an approach is inaccurate for small species populations as it neglects the discrete representation of population values, presents the possibility of negative populations, and does not represent the stochastic nature of biochemical systems. The Stochastic Simulation Algorithm (SSA) developed by Gillespie is able to properly account for these inherent noise fluctuations. Due to the stochastic nature of the Monte Carlo simulations, large numbers of simulations ...


Parameterizable Network-On-Chip Emulation Framework, Jaya Suseela 2010 University of Nevada, Las Vegas

Parameterizable Network-On-Chip Emulation Framework, Jaya Suseela

UNLV Theses, Dissertations, Professional Papers, and Capstones

Networks-on-Chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. But there is no public accessible HDL synthesizable NoC framework which connects industrial level cores and runs real applications on them. Moreover, many challenging research problems remain unsolved at all levels of design abstraction; design exploration of NoC architecture for applications, scheduling and mapping algorithms, evaluation of switching, topology or routing algorithm for efficient execution of application and optimizing communication cost, area, energy etc Solution to solve the above problem calls for the development of synthesizable, parameterizable NoC Framework that would evaluate and implement the above ...


Software Engineering Issues For Mobile Application Development, Tony Wasserman 2010 Carnegie Mellon University

Software Engineering Issues For Mobile Application Development, Tony Wasserman

Tony Wasserman

This paper provides an overview of important software engineering research issues related to the development of applications that run on mobile devices. Among the topics are development processes, tools, user interface design, application portability, quality, and security.


A Single-Chip Ultra-Wideband Based Wireless Sensor Network Node, Nathan R. Schemm 2010 University of Nebraska at Lincoln

A Single-Chip Ultra-Wideband Based Wireless Sensor Network Node, Nathan R. Schemm

Theses, Dissertations, and Student Research from Electrical & Computer Engineering

This dissertation presents the design of a next-generation wireless sensor network node. The node incorporates many new and innovative technologies such as an ultra-wideband radio which allows very low-energy communication, a low-power radiation detection front end, and an efficient implementation of dynamic voltage scaling which improves the energy efficiency of the integrated processor. The complete design is integrated on a single chip for maximum power savings and minimal size.

The ultra-wideband transceiver includes many novel techniques to produce a receiver with low power consumption and fast and accurate packet acquisition and reception. These include the use of a standard symmetric ...


Addressing Computational Complexity Of Electromagnetic Systems Using Parameterized Model Order Reduction, Majid Ahmadloo 2010 University of Western Ontario

Addressing Computational Complexity Of Electromagnetic Systems Using Parameterized Model Order Reduction, Majid Ahmadloo

Electronic Thesis and Dissertation Repository

As operating frequencies increase, full wave numerical techniques such as the finite element method (FEM) become necessary for the analysis of high-frequency and microwave circuit structures. However, the FEM formulation of microwave circuits often results in very large systems of equations which are computationally expensive to solve. The objective of this thesis is to develop new parameterized model order eduction (MOR) techniques to minimize the computational complexity of microwave circuits. MOR techniques provide a mechanism to generate reduced order models from the detailed description of the original FEM formulation. The following contributions are made in this thesis:

1. The first ...


Synthesizing Optimal Fixed-Point Arithmetic For Embedded Signal Processing, Kenneth J. Hass 2010 Bucknell University

Synthesizing Optimal Fixed-Point Arithmetic For Embedded Signal Processing, Kenneth J. Hass

Faculty Conference Papers and Presentations

No abstract provided.


Asynchronous Mips Processors: Educational Simulations, Robert L. Webb 2010 California Polytechnic State University - San Luis Obispo

Asynchronous Mips Processors: Educational Simulations, Robert L. Webb

Master's Theses and Project Reports

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous ...


Polyenvi, Stephen Beard, Josh Engel, Paul Fake, Diego Flores, Alvaro Nunez, Miguel Wong 2010 California Polytechnic State University - San Luis Obispo

Polyenvi, Stephen Beard, Josh Engel, Paul Fake, Diego Flores, Alvaro Nunez, Miguel Wong

Electrical Engineering

Poor indoor air quality is a problem that is recognized by the Environmental Protection Agency (EPA) to cause health issues. In order to raise awareness of this problem, this document outlines the construction of a device that economically measures air quality through five metrics: dust, smoke, ozone, humidity, and temperature. The device integrates with a router to provide users access to information about their indoor air quality anywhere over the internet as well as local access to the data via an LCD mounted on the router. By increasing indoor air quality awareness, this device will aid users in making adjustments ...


A Fully Integrated High-Temperature, High-Voltage, Bcd-On-Soi Voltage Regulator, Benjamin Matthew McCue 2010 University of Tennessee, Knoxville

A Fully Integrated High-Temperature, High-Voltage, Bcd-On-Soi Voltage Regulator, Benjamin Matthew Mccue

Masters Theses

Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a ...


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